RAAAM and the EIC Accelerator: Denser On-Chip Memory Than SRAM

RAAAM Memory Technologies, founded in 2021 and led by co-founder and chief executive Robert Giterman, is headquartered in Petach Tikva, Israel, with an R&D centre in Switzerland, and develops GCRAM, a gain-cell memory meant to replace SRAM, the fast on-chip memory that the EIC report says takes up more than half the area of almost any chip and has stopped shrinking with new manufacturing processes. Its EIC Accelerator project, GCRAM, receives an EU contribution of €2,499,999 and runs from July 2024 to December 2026, according to CORDIS. It aims to qualify GCRAM on a leading-edge foundry process so any chip designer can use it. RAAAM announced €5.25 million of EIC support in total, according to RAAAM.

The first report, covering the first six months, says RAAAM implemented its bitcell in a leading foundry's state-of-the-art FinFET process with about 40 to 50% area reduction versus high-density SRAM, and planned a test chip tape-out in April 2025 with full silicon characterisation in the fourth quarter of 2025, according to CORDIS. In June 2026 Avnet ASIC announced it had become RAAAM's partner for qualifying GCRAM on TSMC's 2-nanometre process, with a customer test chip taped out in March 2026, according to RAAAM. In September 2026 RAAAM and GlobalFoundries announced joint development of a GCRAM test chip on GlobalFoundries' FDX platform.

Where RAAAM Stands Now

In November 2025 RAAAM closed an oversubscribed $17.5 million Series A led by NXP Semiconductors, with a multinational networking company, IAG Capital Partners, the EIC Fund, LiFTT, Alumni Ventures and existing investors, bringing total funding above $24 million, according to RAAAM. It announced a lead licensee in July 2024 and a collaboration with NXP in September 2024. As a private Israeli company, its accounts are not public.

The Technology: Fewer Transistors per Bit

SRAM no longer shrinks at advanced manufacturing nodes, the EIC report says. GCRAM is built from standard CMOS with no extra process steps, so a chip designer can drop it in place of SRAM. RAAAM claims up to 50% less area and up to 10 times lower power; independent silicon data on leading-edge nodes has not been published.

What the EIC Award Promised, and What the Record Shows

The project runs until December 2026, so it is too early to judge it. RAAAM's first timeline, a tape-out in April 2025 and silicon results by the end of 2025, is not confirmed publicly; the 2nm tape-out it announced came in March 2026. Qualification, the project's core deliverable, is ongoing.

1. Bitcell in leading-edge nodeDeliveredFinFET design.
2. Test chip taped outDeliveredTSMC 2nm, March 2026.
3. Silicon characterisationNot publishedPlanned Q4 2025.
4. Full qualificationIn progressAvnet ASIC.

The Money

RAAAM is an EIC award where the equity arrived: the EIC Fund invested alongside NXP in the Series A. Its stake size was not disclosed.

What Cannot Be Checked

Why Europe Should Care

AI chips need ever more on-chip memory, and denser memory saves silicon and power. RAAAM's Swiss R&D centre and its partners NXP and GlobalFoundries link it to Europe's chip ecosystem, though its main qualification work is on TSMC's 2nm process.

The Verdict

RAAAM and the EIC have not been asked for comment for this article. It is based entirely on public records and published statements, linked throughout.